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Synthesis of multiple bus/functional unit architectures implementing neural networks

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2 Author(s)
Haroun, B. ; Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada ; Torbey, E.

An automated architectural synthesis methodology for implementing digital neural networks is presented. The synthesis approach uses heuristics and is based on VLSI multiple-bus/functional-unit architectures with internal parallelism. The synthesis methodologies and tradeoffs as well as the features of the architectures are presented. The architectures resulting from the synthesis tool outperform other architectures for the same applications

Published in:

Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on

Date of Conference:

11-14 Oct 1992