Referenced Items are not available for this document.
An RTL (register level) design verification method that first separates a given design into a datapath and a control circuit and fully utilizes information obtained from the datapath when verifying the control circuit is presented. The method has been successfully applied to the verification of a real 20K-gate chip that performs interface control between processors and networks in a parallel machine. So far, one fifth of the functions of the chip have been verified, in less than a 1 min on SPARC2
Published in:
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Date of Conference: 11-14 Oct 1992
- Page(s):
- 592 - 597
- Meeting Date :
- 11 Oct 1992-14 Oct 1992
- Print ISBN:
- 0-8186-3110-4
- INSPEC Accession Number:
- 4478460
- Conference Location :
- Cambridge, MA
- Digital Object Identifier :
- 10.1109/ICCD.1992.276219
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