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Zero waiting-cycle hierarchical block matching algorithm and its array architectures

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3 Author(s)
Bor-Min Wang ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Jui-Cheng Yen ; Shyang Chang

A new hierarchical block matching algorithm with a novel arrangement of data flow is proposed. Its speed can be as fast as that of the conventional hierarchical block matching algorithms and its prediction quality is very close to the full search algorithm. In order to implement this algorithm, a multiprocessor array architecture for real-time processing is proposed. Due to the novel arrangement of data flow, the limitations of conventional ones will no longer exist. Moreover, the hardware complexity, size of local memory, input bandwidth, and speed performance of the proposed architecture are also analyzed. Finally, the simulation results are given to demonstrate the effectiveness of this new algorithm

Published in:

IEEE Transactions on Circuits and Systems for Video Technology  (Volume:4 ,  Issue: 1 )