By Topic

Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Diaz, C.H. ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; Sung-Mo Kang ; Duvvury, C.

Previous work on electrothermal simulation using network analysis techniques has been of limited use due to the lack of avalanche breakdown modeling capability and the models to efficiently describe the temperature dynamics. Particularly, simulation of electrical overstress (EOS) and electrostatic discharge (ESD), which are important threats to IC reliability, require an accurate description of temperature-dependent device electrical behaviour including breakdown phenomenon. This paper presents electrothermal device models and their implementation in a new circuit-level electrothermal simulator iETSIM. Simulation results for an I/O protection device in an advanced MOS process are presented to demonstrate iETSIM's ability to accurately model device behaviour up to the onset of second breakdown

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:13 ,  Issue: 4 )