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Lower-bound performance estimation for the high-level synthesis scheduling problem

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2 Author(s)
M. Rim ; Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA ; R. Jain

A given behavioral specification can be implemented on a large number of register-transfer level designs. Instead of producing several designs and selecting the best one, synthesis systems may use estimation to reduce the design space. In this paper, we present a new technique for computing a lower-bound completion time for non-pipelined resource-constrained scheduling problem. Given a data flow graph, a set of resources, resource delays and a clock cycle, we derive a lower-bound on the completion time of a schedule. Our technique can handle chaining, multi-cycle operations and pipelined modules. The technique is very fast and experimental results show that it is also very tight

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:13 ,  Issue: 4 )