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16*16 bit parallel multiplier based on 6 K gate array with 0.3 mu m AlGaAs/GaAs quantum well transistors

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13 Author(s)
Thiede, A. ; Fraunhofer Inst. for Appl. Solid State Phys., Freiburg, Germany ; Berroth, M. ; Hurm, V. ; Nowotny, U.
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The design and performance of a 16*16 bit parallel multiplier based on a 6 K gate array will be presented. This LSI semicustom IC demonstrates the high potential of the authors' AlGaAs/GaAs quantum well FETs with a gate length of 0.3 mu m. The best multiplication time measured was 7.2 ns.

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Electronics Letters  (Volume:28 ,  Issue: 11 )