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VLSI implementation of digital channeliser using distributed arithmetic

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2 Author(s)
R. Qi ; Dept. of Electron. & Electr. Eng., Surrey Univ., Guildford, UK ; F. P. Coakley

A VLSI architecture for a digital channeliser based on the time-multiplexed tree filter bank is described, in which the maximum sharing of the arithmetic operations at each stage is achieved. A very efficient implementation of the band-splitting filter is achieved by using distributed arithmetic, allowing a single chip design that does not require multipliers for an 8 channel channeliser.

Published in:

Electronics Letters  (Volume:28 ,  Issue: 11 )