Design of a CMOS analog programmable cellular neural network

The design of an analog programmable CNN architecture with low-power dissipation in a 1.5- mu m CMOS technology is presented. After discussing the design of basic building blocks, the electrical performance of a 10*10 CMOS CNN, consisting of about 8000 MOS transistors, fully simulated at the device level, which can be analog-programmed by varying an external control voltage is discussed. The CNN can perform such functions as noise removal, hole filter, shadow detector, connected component recognition, and edge detector. The power consumption of the circuit is about 60 mW, which is about 1/3 of the power consumption of a previously reported nonprogrammable circuit.<
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