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A low-power static frequency divider circuit in bipolar technology

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6 Author(s)
K. Y. Toh ; IBM, Yorktown Heights, NY, USA ; Y. C. Tzeng ; J. D. Warnock ; E. J. Petrillo
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A low-power silicon bipolar frequency divider circuit using AC-coupled active pull-down emitter-coupled-logic (ECL)-like circuitry is described. The divide-by-eight circuit consists of three identical divide-by-two modules in cascade. The clock is brought in through an emitter-follower, and the output of the divider is buffered through an emitter-follower output stage. The divide-by-two module consists of a pair of master-slave flip-flops. A maximum clocking frequency of 2.5 GHz at a record low power of 1.7 mW per flip-flop has been realized. The performance can be extended to 6 GHz at 5 mW per flip-flop

Published in:

Bipolar/BiCMOS Circuits and Technology Meeting, 1992., Proceedings of the 1992

Date of Conference:

7-8 Oct 1992