Referenced Items are not available for this document.
The authors present a BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers without race problems using a Wallace tree reduction architecture. With the BiCMOS dynamic full adder circuit, an 8×8 multiplier designed based on a 2-μm BiCMOS technology showed a 6x improvement in speed as compared to a CMOS static circuit
Published in:
Bipolar/BiCMOS Circuits and Technology Meeting, 1992., Proceedings of the 1992
Date of Conference: 7-8 Oct 1992
- Page(s):
- 191 - 194
- Meeting Date :
- 07 Oct 1992-08 Oct 1992
- Print ISBN:
- 0-7803-0727-5
- INSPEC Accession Number:
- 4575413
- Conference Location :
- Minneapolis, MN
- Digital Object Identifier :
- 10.1109/BIPOL.1992.274053
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