By Topic

Architecture of a high speed Reed-Solomon decoder

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Iwaki, T. ; Sharp Corp., Nara, Japan ; Tanaka, T. ; Yamada, E. ; Okuda, T.
more authors

The authors propose an architecture for an error correction circuit suitable for high-rate data decoding of the Reed-Solomon code. It features a multiple-error correction capability of 4 errors or 8 erasures. The operational steps for multiple-error decoding are reduced by a 4-stage pipeline and a superscalar processor of a Galois field. The experimental circuit's 16 Mbyte/s rate of data decoding is sufficient for compressed video signals of high-definition as well as those of standard-definition TVs

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:40 ,  Issue: 1 )