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Architecture of a high speed Reed-Solomon decoder

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5 Author(s)
Iwaki, T. ; Sharp Corp., Nara, Japan ; Tanaka, T. ; Yamada, E. ; Okuda, T.
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The authors propose an architecture for an error correction circuit suitable for high-rate data decoding of the Reed-Solomon code. It features a multiple-error correction capability of 4 errors or 8 erasures. The operational steps for multiple-error decoding are reduced by a 4-stage pipeline and a superscalar processor of a Galois field. The experimental circuit's 16 Mbyte/s rate of data decoding is sufficient for compressed video signals of high-definition as well as those of standard-definition TVs

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Consumer Electronics, IEEE Transactions on  (Volume:40 ,  Issue: 1 )