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Rate-optimal DSP synthesis by pipeline and minimum unfolding

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2 Author(s)
Lih-Gwo Jeng ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Liang-Gee Chen

This paper presents a rate-optimal scheduling for real-time DSP algorithms. By using pipelining and unfolding techniques, the parallel characteristics of recursive DSP algorithms can be exploited. A novel unfolding technique is developed to unravel all concurrency in the recursive data flow graph. A perfect rate unfolded data flow graph is also introduced, which can cause a fully static rate optimal functional pipeline schedule. Experimental results have shown that the proposed method can always yield rate-optimal designs with a smaller unfolding factor compared to previous studies.<>

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:2 ,  Issue: 1 )