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Browse Journals & Magazines > Solid-State Circuits, IEEE Jo ...> Volume:23 Issue:1 Help

A high-speed CMOS comparator for use in an ADC

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3 Author(s)
McCarroll, B.J. ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; Sodini, C.G. ; Hae-Seung Lee

A dynamic latch preceded by an offset-cancelled amplifier is used in the 3- mu m CMOS comparator to obtain a response time of 43 ns. The offset-cancelled amplifier reduces the input-referred offset so that medium-resolution analog-to-digital converters (ADCs) can be built with this comparator. The use of pipelining within the comparator enables the offset cancellation to be done as the dynamic latch is enabled. Power and area are optimally distributed within the amplifier to minimize response time.<>

Published in:
Solid-State Circuits, IEEE Journal of  (Volume:23 ,  Issue: 1 )

Date of Publication: Feb. 1988

Page(s):
159 - 165
ISSN :
0018-9200
INSPEC Accession Number:
3132896
Digital Object Identifier :
10.1109/4.273
Product Type:
Journals & Magazines
Date of Current Version :
06 August 2002
Issue Date :
Feb. 1988
Sponsored by :
IEEE Solid-State Circuits Society

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