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An architecture for high-performance/small-area multipliers for use in digital filtering applications

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3 Author(s)
Kwentus, A.Y. ; Dept. of Electr. Eng., California State Univ., Los Angeles, CA, USA ; Hing-Tsun Hung ; Willson, A.N., Jr.

A multiplier architecture and encoding scheme well suited for programmable digital filtering applications is described. The multiplier's partial product recoding scheme uses only simple multiplexers and takes advantage of a RAM that stores filter coefficients. We use an optimized 20-transistor full-adder cell in the carry-save adder array, and a carry-select vector-merge adder produces the final output. An integrated circuit comprising an ll-b by ll-b multiplier using second-order recoding has been fabricated in 2-μm CMOS technology. It operates in 22 ns and its core occupies 1.53 mm2. Also, an ll-b by 16-b multiplier using third-order recoding has been fabricated through MOSIS in 1.2-μm CMOS technology. Its core occupies 0.9 mm2 and it operates in 19 ns

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:29 ,  Issue: 2 )

Date of Publication:

Feb 1994

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