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Offset compensating bit-line sensing scheme for high density DRAM's

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3 Author(s)
Y. Watanabe ; East Fishkill Fac., IBM Corp., Hopewell Junction, NY, USA ; N. Nakamura ; S. Watanabe

This paper describes a new bit-line sensing scheme that minimizes the sensitivity degradation caused by the electrical imbalance in a sense amplifier composed of scaled-down transistors. The new sensing scheme incorporates an offset compensating technique in a direct bit-line sensing scheme using a current-mirror differential amplifier. The compensation is performed by means of a simple negative feedback method that accomplishes cancellation of the total electrical imbalance in the sense amplifier with a short presetting time. The features of the circuit have been examined using simple DRAM test chips fabricated with a 0.5 μm CMOS process. Experimental results indicate that the magnitude of the imbalance of the sense amplifier is reduced to one-sixth by introducing the offset compensating scheme as compared to the conventional sensing scheme

Published in:

IEEE Journal of Solid-State Circuits  (Volume:29 ,  Issue: 1 )