Cart (Loading....) | Create Account
Close category search window
 

A general architecture of ATM switching networks which are non-blocking at call level

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Sezaki, K. ; Inst. of Ind. Sci., Tokyo Univ., Japan ; Yasuda, Y.

The simplest approach to compose a very large scale asynchronous transfer mode switching network is to compose it with only buffered unit switches. A practical architecture of such a switching network is studied and a generalized parallel delta network is proposed. It is composed by only one kind of n×n unit switch. The number of stages does not necessarily depend on the scale of the entire switching network. It is nonblocking at call level, and good cell-level traffic performance is expected. It is also very fault tolerant

Published in:

TENCON '92. ''Technology Enabling Tomorrow : Computers, Communications and Automation towards the 21st Century.' 1992 IEEE Region 10 International Conference.

Date of Conference:

11-13 Nov 1992

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.