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Systematic architecture design for highly parallel image processing array

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3 Author(s)
Isshiki, T. ; Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan ; Takeuchi, Y. ; Kunieda, H.

A methodology for designing the architecture of the processor array for a wide class of image processing algorithms is proposed. A concept of spatially expanding the signal flow graph (SFG) description which enables handling the problem as merely one-dimensional signal processing is used in constructing the methodology. The problem of I/O interface which is critical in real-time processing is also considered

Published in:

Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on

Date of Conference:

9-12 Aug 1992