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Noise performance optimization design for high-speed analog-to-digital converters

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2 Author(s)
Sandage, R.W. ; Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA ; Burns, S.G.

An fT=8.5 GHz NPN bipolar junction transistor (BJT)-based application specific integrated circuit (ASIC) comparator, for use in analog-to-digital converters (ADCs) is designed for optimum noise performance using process-derived model parameters including base spreading resistance, device geometry, and spot noise figure contours. The relationship between sensitivity of the comparator and equivalent input noise (Eni) and offset voltage (VOS) is presented. Eni and VOS must be minimized for a high-resolution comparator. An equivalent input noise voltage of less than 1.2 nV/√Hz is predicted and measured, which is approximately 1/3 that obtained from typical low-noise ADC comparators

Published in:

Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on

Date of Conference:

9-12 Aug 1992