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A VLSI implementation of an interface for a dual protocol high speed active bus

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5 Author(s)
Ng, S. ; Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA ; Peursem, J.V. ; Hassoun, M. ; Davis, J.
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A new multiple bus architecture with an active backplane has been developed. The authors examine the existing data transfer protocol for part of the architecture, then develop the complete data transfer protocol for the whole architecture. They also prove the feasibility of bridging a system using this new bus-based architecture to an existing system which uses a different communication network. As an example of this capability, an implementation of a bridge chip for the AN/AYK-14(V) military airborne computer system bus is described

Published in:

Circuits and Systems, 1992., Proceedings of the 35th Midwest Symposium on

Date of Conference:

9-12 Aug 1992