Referenced Items are not available for this document.
The hardware infrastructure, display system, digital signal processor, array and host-computer control software components developed in a joint project are described. A 64-bit wide implementation of Futurebus+ provides backplane transfer rates of 500 to 700 MByte/s for data flow between array processors, memory, and display modules all being controlled from a host computer workstation. The two million pixel display module supports viewing rates exceeding 36 images per second for single or multiple image streams. Processing is guided by the operator using ball-type or glove-type interactive devices by viewing animation-rate computed images displayed on the screen. One of the hardware modules includes a thirty-two TMS320C40 processor array capable of a peak computation rate of 1.6 GFLOPS and a sustained rate of about 1 GFLOPS on the scan-line oriented algorithms for which the architecture has been optimized.
Published in:
System Sciences, 1993, Proceeding of the Twenty-Sixth Hawaii International Conference on
(Volume:i
)
Date of Conference: 5-8 Jan 1993
- Page(s):
- 106 - 115 vol.1
- Print ISBN:
- 0-8186-3230-5
- INSPEC Accession Number:
- 4602107
- Digital Object Identifier :
- 10.1109/HICSS.1993.270754
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
