Skip to Main Content
The authors present an optimization approach to synthesizing digital signal processing (DSP) specific architectures utilizing programmable VLSI technologies. A new integer programming (IP) model is presented that supports simultaneous scheduling, allocation, and retiming or loop winding. The IP model is used to map a DSP application to a high-speed application-specific architecture and to map multiple DSP applications to a programmable architecture. The same model can also be used to map an application to multiple chips. Results show that the optimization approach synthesizes architectures that are 10% to 24% faster with up to 12% higher throughputs than previously published architectures.