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Optimal mapping of DSP application to architectures

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2 Author(s)
Gebotys, C.H. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Gebotys, R.J.

The authors present an optimization approach to synthesizing digital signal processing (DSP) specific architectures utilizing programmable VLSI technologies. A new integer programming (IP) model is presented that supports simultaneous scheduling, allocation, and retiming or loop winding. The IP model is used to map a DSP application to a high-speed application-specific architecture and to map multiple DSP applications to a programmable architecture. The same model can also be used to map an application to multiple chips. Results show that the optimization approach synthesizes architectures that are 10% to 24% faster with up to 12% higher throughputs than previously published architectures.

Published in:

System Sciences, 1993, Proceeding of the Twenty-Sixth Hawaii International Conference on  (Volume:i )

Date of Conference:

5-8 Jan 1993