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Minimum skew multiple clock routing in synchronous ASIC systems

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3 Author(s)
Khan, W. ; Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA ; Hossain, M. ; Sherwani, N.

The problem of routing in the multiple clock environment is more complicated than a single clock environment. An efficient algorithm to obtain minimum skew layout for two clocks in a synchronous system is presented. The algorithm is tested on several industrial benchmarks with promising results. The routing layouts achieve almost zero skew, while using a minimum wire length for multiple clock routing

Published in:

ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International

Date of Conference:

21-25 Sep 1992