By Topic

Minimum skew multiple clock routing in synchronous ASIC systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
W. Khan ; Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA ; M. Hossain ; N. Sherwani

The problem of routing in the multiple clock environment is more complicated than a single clock environment. An efficient algorithm to obtain minimum skew layout for two clocks in a synchronous system is presented. The algorithm is tested on several industrial benchmarks with promising results. The routing layouts achieve almost zero skew, while using a minimum wire length for multiple clock routing

Published in:

ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International

Date of Conference:

21-25 Sep 1992