By Topic

Use of VHDL synthesis in an advanced digital design course

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
B. Reese ; Dept. of Electr. Eng., Mississippi State Univ., MS, USA

A VHSIC hardware description language (VHDL) synthesis tool is used for an advanced digital design course. The tool has the capability of synthesizing sequential elements (flip-flops) as well as combinational logic. The tool gives students the capability of practising a true top-down design methodology. Synthesis implementation targets include the ITD standard cell library (Octtools), Xilinx field programmable gate array (FPGA), Actel FPGA, and Altera FPGA

Published in:

ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International

Date of Conference:

21-25 Sep 1992