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A fuzzy neural network chip based on systolic array architecture

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3 Author(s)
Jiahn Jung Chen ; Inst. of Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Yau-Hwang Kuo ; Cheng-I Kao

A neural network model using a fuzzy classification concept, called FNN, is proposed. The design of an ASIC that implements that FNN model is presented. The chip architecture is based on a one-dimensional systolic array architecture, which provides a low-cost and high-performance parallel inference scheme. The high-level synthesis technique is adopted to design the ASIC, and VHSIC hardware description language (VHDL) is used to model it at the behavior domain

Published in:

ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International

Date of Conference:

21-25 Sep 1992