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A memory to read out and write a block of words via one memory access and its application to increase processor and cache performance

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1 Author(s)
I. Polkovnikov ; San Francisco, CA, USA

A memory architecture for reading out a block of bits, bytes, or words in parallel via one memory access beginning with any address location is presented. Discussed topics are: a processor reading a several-word instruction via one memory access and its comparison with a RISC one; transformation of an existing CISC architecture to a superscalar one reading a set of instructions in parallel; instructions having any size of opcode, immediate data, and address displacement; and a cache updating by several words in parallel

Published in:

Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on

Date of Conference:

26-28 Oct 1992