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Performance analysis for a two level cache system

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2 Author(s)
Mekhiel, N.N. ; Dept. of Electr. Eng., Ryerson Polytech. Inst., Toronto, Ont., Canada ; McCrackin, D.C.

A simple analytical model for a two-level cache system is developed. The model evaluates the effect of different parameters on the overall system performance. It includes three different designs that are generated from using the write through and the write back methods for the first and the second level cache. The model defines an improved write policy for write back. During a write miss to a clean block the model can write to the cache similar to a write hit. The model shows that increasing the block size for the first level cache could decrease system performance, and the size increase of the second level cache has a greater effect on the performance when the system uses a larger first level cache

Published in:

Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on

Date of Conference:

26-28 Oct 1992