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Design of easily testable VLSI arrays for discrete cosine transform

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3 Author(s)
Shyue-Kung Lu ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Cheng-Wen Wu ; Juo, S.-Y.

A design-for-testability approach based on the M-testability conditions is applied to the bit-level VLSI systolic arrays for discrete cosine transform (DCT), which guarantee 100% single-cell-fault testability with a minimum number of test patterns. A hardware overhead of no more than 6% is sufficient to make the DCT arrays M-testable. The resulting number of test patterns is only 16, regardless of the size of the DCT array and the internal word length. DCT array testing using the module-fault model also is discussed. M-testable arrays are proposed. An offline fault diagnosis scheme which detects and locates any faulty module in the DCT array by self-comparison is presented

Published in:

Signals, Systems and Computers, 1992. 1992 Conference Record of The Twenty-Sixth Asilomar Conference on

Date of Conference:

26-28 Oct 1992