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Browse Journals & Magazines > Semiconductor Manufacturing, ...> Volume:6 Issue:4 Help

Optimal life testing schedule for multiple types of integrated circuits

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1 Author(s)
Leung, Y.-W. ; Dept. of Inf. Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong

Life testing of highly reliable integrated circuits (ICs) is a time-consuming process because it usually takes a long time before an IC fails. Several methods have been proposed in the literature to reduce the time required for testing one type of IC. The author considers the problem of estimating the mean life of I types of IC (I>1). Assuming that the lifetime distribution of the ICs is exponential and at most N ICs can be tested concurrently, it is shown that the optimal life testing schedule that requires the smallest mean testing time is to test N ICs of type 1, then test N ICs of type 2,. . . and finally test N ICs of type I

Published in:
Semiconductor Manufacturing, IEEE Transactions on  (Volume:6 ,  Issue: 4 )

Date of Publication: Nov 1993

Page(s):
318 - 323
ISSN :
0894-6507
INSPEC Accession Number:
4628421
Digital Object Identifier :
10.1109/66.267641
Product Type:
Journals & Magazines
Date of Current Version :
06 August 2002
Issue Date :
Nov 1993
Sponsored by :
IEEE Components, Packaging and Manufacturing Technology Society

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