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A SIMD-systolic architecture and VLSI chip for the two-dimensional DCT and IDCT

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2 Author(s)
Chen-Mie Wu ; Dept. of Electron. Eng., Nat. Taiwan Inst. of Technol., Taipei, Taiwan ; Chiou, A.

The authors present a SIMD-systolic architecture for computing the two-dimensional discrete cosine transform (2D-DCT) and inverse discrete cosine transform (2D-IDCT). With four processing elements and a dynamic switching network, this architecture can compute 2D-DCT or 2D-IDCT for 8×8 blocks in sixty-four internal clock cycles (or 128 I/O clock cycles). Currently, based on a 0.8 μm SPDM CMOS technology, a forty-pin VLSI chip has been designed and fabricated for such an architecture. Testing results have shown that the chip is functionally correct and can compute 2D-DCT or 2D-IDCT for 8×8 blocks in 8.2 μs

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Consumer Electronics, IEEE Transactions on  (Volume:39 ,  Issue: 4 )