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A single chip VLSI chrominance/luminance separator based on a silicon compiler

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7 Author(s)

The authors present a single-chip VLSI chrominance/luminance (Y/C) separator that is economically fabricated for NTSC TV signals at 13.5-MHz CCIR standard sampling rate. In order to realize compactness and low power dissipation, two FIR filter architectures and a multiplier structure are proposed. A silicon compiler, which uses these structures, also contributes to fast and error-free VLSI development. The Y/C separator chip has 10.4-mm×11.7-mm die size and attains about 860-MOPS operating speed

Published in:

Acoustics, Speech, and Signal Processing, 1989. ICASSP-89., 1989 International Conference on

Date of Conference:

23-26 May 1989