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Block digital signal processor balances performance and complexity

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6 Author(s)
Khaitan, B. ; Hitachi Micro Syst. Inc., San Jose, CA, USA ; Blasco, R. ; Patel, C.N. ; Chan, K.
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A DSP (digital signal processor) VLSI with a price/performance ratio enhanced by using properties unique to DSP is presented. The objective was to achieve much of the performance of this third-generation DSP chip at a substantially lower system cost. The device provides a 50-ns cycle time with single-level pipelining, and is packaged in a 68-pin plastic leaded chip carrier. The device is fabricated in a 1-μm CMOS process. Attention is given to the system environment, the DSP architecture, and the block sample processing

Published in:

Acoustics, Speech, and Signal Processing, 1989. ICASSP-89., 1989 International Conference on

Date of Conference:

23-26 May 1989