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A new dynamic test vector compaction for automatic test pattern generation

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2 Author(s)
Ayari, B. ; Ecole Polytech., Montreal, Que., Canada ; Kaminska, B.

A new approach for dynamic test vector compaction, for combinational logic circuits, called COMPACT, is proposed. A new data structure of test vectors permits easy verification of compactability between test vectors with minimal memory requirements. Experimental results obtained by adding the proposed algorithm to a simple PODEM program and applying it to the ISCAS-85 benchmark circuits are presented. The resulting test vector reduction is up to 40% for small circuits and around 50% for the large circuits (over 1000 gates)

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:13 ,  Issue: 3 )