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A two-level on-chip memory for video signal processor

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3 Author(s)
Chia-Hsing Lin ; Inst. of Electron. Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Jen-Sheng Hung ; Chein-Wei Jen

The authors propose an on-chip memory architecture for video signal processor (VSP). According to the nature of different data locality in video source coding applications, the memory adopts a novel two-level scheme for making trade-off between capacity and flexibility. The upper level, Memory A, provides enough storage capacity to reduce the impact on the limitation of chip I/O bandwidth, and the lower level, Memory B, provides enough data parallelism and flexibility to meet the requirements of multiple reconfigurable pipeline function units in a single VSP chip. They have designed a prototype memory using 1.2- mu m SPDM SRAM technology.

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VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on

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