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The authors propose an on-chip memory architecture for video signal processor (VSP). According to the nature of different data locality in video source coding applications, the memory adopts a novel two-level scheme for making trade-off between capacity and flexibility. The upper level, Memory A, provides enough storage capacity to reduce the impact on the limitation of chip I/O bandwidth, and the lower level, Memory B, provides enough data parallelism and flexibility to meet the requirements of multiple reconfigurable pipeline function units in a single VSP chip. They have designed a prototype memory using 1.2- mu m SPDM SRAM technology.