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Yield improvement for a 3.5-ns BiCMOS technology in a 200-mm manufacturing line

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15 Author(s)
Bomy Chen ; IBM Technol. Prod. Essex Junction, VT, USA ; Hook, T. ; Starkey, G. ; Bhattacharyya, A.
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Various issues pertinent to producing high volumes of a high-end BiCMOS technology in a 200-mm manufacturing line are described. The technology consists of a baseline 0.8- mu m CMOS process with four levels of metal and 0.45- mu m Leff FETs, to which has been added a boron-implanted precision resistor, a 14-GHz vertical NPN with As-doped polysilicon, and an antimony-doped subcollector. Chips fabricated in the technology include a 3.5-ns 576 K BiCMOS SRAM and a 200 K BiCMOS gate array with a 180-ps gate delay. Yield detractors unique to the integration of the BiCMOS elements are discussed and solutions presented. In particular, collector-emitter shorts, a spurious polysilicon filament, management of the critical emitter window image, and modulation of the titanium silicide/silicon interfacial resistance are considered.

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VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on

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