Referenced Items are not available for this document.
A two-level pipelined systolic array chip for the discrete cosine transform (DCT) is presented. This chip is based on a new memory-based systolic algorithm which not only uses small ROMs and adders to realize the multiplications but also owns good data locality. Therefore, this chip possesses outstanding performance in hardware cost, computing speeds, the number of I/O channels, and the I/O bandwidth.
Published in:
VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on
Date of Conference: 1993
- Page(s):
- 199 - 203
- Meeting Date :
- 12 May 1993-14 May 1993
- Print ISBN:
- 0-7803-0978-2
- INSPEC Accession Number:
- 4590170
- Conference Location :
- Taipei, Taiwan
- Digital Object Identifier :
- 10.1109/VTSA.1993.263606
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