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A two-level pipelined systolic array chip for computing the discrete cosine transform

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3 Author(s)
Jiun-In Guo ; Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chi-Min Liu ; Chein-Wei Jen

A two-level pipelined systolic array chip for the discrete cosine transform (DCT) is presented. This chip is based on a new memory-based systolic algorithm which not only uses small ROMs and adders to realize the multiplications but also owns good data locality. Therefore, this chip possesses outstanding performance in hardware cost, computing speeds, the number of I/O channels, and the I/O bandwidth.

Published in:

VLSI Technology, Systems, and Applications, 1993. Proceedings of Technical Papers. 1993 International Symposium on

Date of Conference:

1993