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Total dose radiation hardening and testing issues of CMOS static memories

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2 Author(s)
Hensley, R. ; Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA ; Srivastava, A.

A radiation hardened circuit should be both processed and designed for hardness. It is demonstrated that the MOSIS two micron CMOS technology exhibits radiation hardened properties, making it particularly suitable for a design methodology in which circuitry is added to compensate for the radiation induced degradation of the zero input noise margin. The non-ideal behavior of the compensation circuitry is explained and application of the circuitry in a static RAM cell is explored

Published in:

Memory Testing, 1993., Records of the 1993 IEEE International Workshop on

Date of Conference:

9-10 Aug 1993