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Design validation: comparing theoretical and empirical results of design error modeling

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2 Author(s)
Sungho Kang ; Motorola Inc., Austin, TX, USA ; Szygenda, S.A.

To use simulation for design verification, designers need a confidence measure for a given set of simulation patterns, specifically for cases in which only a subset of the possible patterns is used. The authors derive a measure of design verification coverage based on the number of design errors detected in a theoretical analysis of a circuit. To verify the theoretical analysis, they simulate errors and compare the results.<>

Published in:

Design & Test of Computers, IEEE  (Volume:11 ,  Issue: 1 )