By Topic

Two complementary approaches for microcode bit optimization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
In-Cheol Park ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea ; Se-Kyoung Hong ; Chong-Min Kyung

In the design of microprogrammed processors, the minimization of microcode width is very crucial to reduce the required microcode ROM area. The paper suggests two different procedures which are complementary in nature: first an integer linear programming formulation which guarantees an optimal solution for small or medium size problems; and second, a heuristic algorithm based on the graph bipartitioning to deal with large size problems. Experimental results show that the proposed heuristic algorithm yields near-optimal solutions with polynomial time complexity

Published in:

Computers, IEEE Transactions on  (Volume:43 ,  Issue: 2 )