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VIPER: a VLIW integer microprocessor

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4 Author(s)
J. Gray ; Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA ; A. Naylor ; A. Abnous ; N. Bagherzadeh

This paper describes the design and implementation of a very long instruction word (VLTW) microprocessor. The VLIW integer processor (VIPER) contains four pipelined functional units and can achieve 0.25-cycle-per-instruction performance. The processor is capable of performing multiway branch operations, two load/store operations, or up to four ALU operations in each clock cycle, with full register file access to each functional unit. Designed in twelve months, the processor is integrated with an instruction cache controller and a data cache, requiring 450,000 transistors and a die size of 12.9 mm×9.1 mm in a 1.2-μm technology

Published in:

IEEE Journal of Solid-State Circuits  (Volume:28 ,  Issue: 12 )