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A monolithic 480 Mb/s parallel AGG/decision/clock-recovery circuit in 1.2-μm CMOS

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2 Author(s)
Hu, T.H. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Gray, P.R.

A parallel architecture for high-data-rate AGC/decision/clock-recovery circuit, recovering digital NRZ data in optical-fiber receivers, is described. Improvement over traditional architecture in throughput is achieved through the use of parallel signal paths. An experimental prototype, fabricated in a 1.2-μm double-poly double-metal n-well CMOS process, achieves a maximum bit rate of 480 Mb/s. The chip contains variable gain amplifiers, clock recovery, and demultiplexing circuits. It yields a BER of 10-11 with an 18 mVp-p differential input signal. The power consumption is 900 mW from a single 5 V supply

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:28 ,  Issue: 12 )