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A 15-b 1-Msample/s digitally self-calibrated pipeline ADC

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3 Author(s)
Karanicolas, A.N. ; Dept. of Electr. Eng., Massachusetts Inst. of Technol., Cambridge, MA, USA ; Hae-Seung Lee ; Barcrania, K.L.

A 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of -90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was measured to be within ±0.25 LSB at 15 b, and the INL was measured to be within ±1.25 LSB at 15 b. The die area is 9.3 mm×8.3 mm and operates on ±4-V power supply with 1.8-W power dissipation. The ADC is fabricated in an 11-V, 4-GHz, 2.4-μm BiCMOS process

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:28 ,  Issue: 12 )

Date of Publication:

Dec 1993

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