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A high-performance CMOS redundant binary multiplication-and-accumulation (MAC) unit

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3 Author(s)
Xiaoping Huang ; Dept. of Electr. Eng., San Jose State Univ., CA, USA ; Wen-Jung Liu ; Wei, B.W.Y.

This paper describes the design of a pipelined CMOS 16×16 redundant binary multiplication-and-accumulation (MAC) unit. The MAC unit uses a novel coding scheme for representing binary signed digits. The coding, integrated with the modified Booth algorithm, produces a factor of four reduction in the number of summands feeding the adder tree without preprocessing. The consequent chip layout is compact and small. Furthermore, the MAC's pipeline stages are balanced, resulting in a clock rate exceeding 200 MHz with 0.8-μm two-level metal CMOS technology

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Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on  (Volume:41 ,  Issue: 1 )