A new technique for forming a shallow link base in a double polysilicon bipolar transistor

A new technique is presented for forming a shallow link base in a double polysilicon bipolar transistor. This method is easily integrated into an advanced BiCMOS process, making use of a disposable polysilicon spacer technology for MOSFET LDD formation. This new scheme allows independent optimization of active and link base regions while providing improvements in base-emitter breakdown and resistance to bipolar hot carrier degradation.<
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