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Balanced high-speed residue number VLSI multiplier with error detection

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2 Author(s)
Lo, H.-Y. ; Dept. of Inf. Eng., Feng-Chia Univ., Tai-Chung, Taiwan ; Yang, T.C.

A balanced residue number VLSI multiplier is proposed which eliminates the extra delay for an unbalanced residue multiplier. The number of adding stages used in the VLSI multiplier is reduced from three to two. The authors also describe how redundant residue number system (RNS) properties can be used for error detection. These improvements allow a residue multiplier with a 48-72 bit dynamic range, to perform 3.3 M multiplication/s without pipelining or 10 M multiplication/s with pipelining

Published in:

Circuits, Devices and Systems, IEE Proceedings G  (Volume:138 ,  Issue: 3 )