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Analysis of a fault-tolerance scheme for processor ensembles

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2 Author(s)
Upadhyaya, S.J. ; State Univ. of New York, Buffalo, NY, USA ; Chakravarty, S.

The authors analyze a locally redundant scheme (LR scheme) for designing fault-tolerant processor ensembles. A switching structure for reconfiguration is presented, and a detailed model for the yield analysis off the LR scheme that takes into account processor, switch, and link failures is developed. A negative binomial distribution is used for the yield statistics, as it best fits the empirical data. This model is used to compare the yields (with and without fault tolerance) of some architectural topologies. A dynamic analysis of the effect of residual redundancy on the improvement of operational system reliability is presented. The analysis reveals an appreciable improvement in the yield and operational system-reliability when the LR scheme is used. This analysis includes the reliability of switches and links, unlike previous analyses of fault-tolerant schemes. The empirical results show that ignoring switch reliability could result in an appreciable overestimate of system reliability

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Reliability, IEEE Transactions on  (Volume:41 ,  Issue: 2 )