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A quantitative evaluation of cache types for high-performance computer systems

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3 Author(s)
Wu, C.E. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Hsu Yarsun ; Liu, Yew-Huey

Parallel accesses to the table lookaside buffer (TLB) and cache array are crucial for high-performance computer systems, and the choice of cache types is one of the most important factors affecting cache performance. The authors classify caches according to both index and tag. Since both index and tag could be either virtual (V) or real (R), their classification results in four combinations or cache types. The real address caches with virtual tags for high-performance computer systems in this study are prediction-based, since index bins are generated from a small array and predictions could be false. As a result, they also discuss and evaluate real address MRU caches with real tags, and propose virtually indexed MRU caches with real tags. Each of the four cache types and MRU caches are discussed and evaluated using trace-driven simulation. The results show that a virtually indexed MRU cache with real tags is a good choice for high-performance computer systems

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Computers, IEEE Transactions on  (Volume:42 ,  Issue: 10 )