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Use of redundant binary representation for fault-tolerant arithmetic array processors

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2 Author(s)
Piuri, V. ; Dept. of Electron., Politecnico di Milano, Italy ; Stefanelli, R.

The authors present a novel approach to online error detection in an arithmetic array processor for very large computing applications. The use of redundant binary representation makes it possible to design strongly fault-secure architectures with respect to unidirectional stuck-at faults on multiple gate input and/or output lines. Online fault localization is also considered for fast array reconfiguration. Enhanced architectures have been proposed to identify the position of faulty elements in the regular array concurrently with the nominal computation. The proposed approach has been evaluated for a class of arrays which can be adopted in a wide spectrum of applications in digital signal and image processing and in matrix operations

Published in:

Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Date of Conference:

3-5 Oct 1988