Novel ASIC architecture and synthesis methodologies for future multiplexed datapath designs

An overview is presented of the main objectives and current achievements of the architecture synthesis work within part of the Basic Research Action ASCIS (architecture synthesis for complex integrated systems) project. The main goal of this work is to contribute to the solution of one of the major bottlenecks restricting the use of ASICs in industrial systems, namely, the lack of efficient design methodologies and corresponding CAD techniques which support the development of cost-effective application-specific architectures for given throughput or latency. The following areas of the project are emphasized: novel design methodologies and CAD techniques for partitioning, memory management, allocation, binding and scheduling; generic global optimization techniques to support those synthesis approaches; and performance-driven controller synthesis