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Design methodology of mapping iterative algorithms on piecewise regular processor arrays

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3 Author(s)
Soudris, D.J. ; Dept. of Electr. Eng., Patras Univ., Greece ; Birbas, M.K. ; Goutis, C.E.

A systematic framework for mapping a class of iterative algorithms onto processor array architectures is presented. The iterative algorithm is directly mapped on the array without the requirement of transforming it into any intermediate form, such a uniform recurrent equation (URE). The principles of Lamport's coordinate method are used. The important subclass of algorithms known as weak single assignment codes (WSACs) is treated in an optimal way. Due to the structure of the algorithm and/or the multidimensional mapping, the resulting architectures can be either regular arrays (RAs) or piecewise regular arrays (PRAs)

Published in:

CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.

Date of Conference:

13-16 May 1991