Referenced Items are not available for this document.
A tool to generate target fault sets for fault simulation and test pattern generation is described. It can deal with circuits described hierarchically and at multiple levels of abstraction (switch, gate, and register transfer), using a uniform fault model and a fast collapsing algorithm. Whenever possible, structurally undetectable faults are identified. A flexible user-friendly interface provides hierarchical, functional, and statistical selection commands to customize a fault set according to the user's needs
Date of Conference: 13-16 May 1991
- Page(s):
- 219 - 223
- Meeting Date :
- 13 May 1991-16 May 1991
- Print ISBN:
- 0-8186-2141-9
- INSPEC Accession Number:
- 4183208
- Conference Location :
- Bologna
- Digital Object Identifier :
- 10.1109/CMPEUR.1991.257385
- Product Type:
- Conference Publications
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