Handling faults in a VLSI CAD environment

A tool to generate target fault sets for fault simulation and test pattern generation is described. It can deal with circuits described hierarchically and at multiple levels of abstraction (switch, gate, and register transfer), using a uniform fault model and a fast collapsing algorithm. Whenever possible, structurally undetectable faults are identified. A flexible user-friendly interface provides hierarchical, functional, and statistical selection commands to customize a fault set according to the user's needs.<
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